430-4140/01 – Digital Systems with FPGAs (DSF)

Gurantor departmentDepartment of Applied ElectronicsCredits5
Subject guarantorIng. Martin Sobek, Ph.D.Subject version guarantorIng. Martin Sobek, Ph.D.
Study levelundergraduate or graduateRequirementOptional
Year1Semestersummer
Study languageCzech
Year of introduction2024/2025Year of cancellation
Intended for the facultiesFEIIntended for study typesFollow-up Master
Instruction secured by
LoginNameTuitorTeacher giving lectures
SOB060 Ing. Martin Sobek, Ph.D.
Extent of instruction for forms of study
Form of studyWay of compl.Extent
Full-time Credit and Examination 2+3
Part-time Credit and Examination 10+12

Subject aims expressed by acquired skills and competences

After completing the course, the student is able to define the basic requirements for digital systems in a wide area of applied electronics, especially for power converter control applications as well as data processing in real-time systems. He can independently realize the design of a digital system in one of the HDLs and implement it in programmable gate arrays. The knowledge gained forms part of the knowledge of an engineer with a focus on the field of applied electronics.

Teaching methods

Lectures
Experimental work in labs

Summary

The subject develops basic knowledge of digital technology and logic circuits. It focuses on the analysis of digital systems and their description using HDL. It deals with the design of individual parts of a digital system for applications in industrial and commercial electronics. The properties of a digital system are presented using simple examples that allow one to penetrate the field of system design and description using HDL.

Compulsory literature:

BHASKER, Jayaram. A verilog HDL primer. 3rd ed. Allentown: Star Galaxy Publishing, c2005. ISBN 0-9650391-6-1. CILETTI, Michael D. Advanced digital design with the Verilog HDL. Prentice Hall Xilinx design series. Upper Saddle River: Prentice Hall, c2003. ISBN 0-13-089161-4.

Recommended literature:

WILSON, Peter R. Design recipes for FPGAs: using Verilog and VHDL. Online. Second edition. Amsterdam: Elsevier/Newnes, 2016. ISBN 9780080971360. [cit. 2024-02-27]. WAKERLY, John F. Digital design: principles and practices. 4th ed. Upper Saddle River: Pearson Prentice Hall, c2006. ISBN 0-13-186389-4.

Way of continuous check of knowledge in the course of semester

Continuous study control: Control tests No. 1 and No. 2. Credit conditions: Participation in laboratory teaching (100%). Submission of measurement protocols. Completion of all control tests on time. Obtaining at least 25 points. Point evaluation of exercises - maximum 40 points, test T1 - maximum 10 points, test T2 - maximum 10 points, laboratory tasks - maximum 20 points.

E-learning

Other requirements

There are no other requirements for a student

Prerequisities

Subject has no prerequisities.

Co-requisities

Subject has no co-requisities.

Subject syllabus:

Lectures: Digital systems, basic requirements for a digital system, meaning and use of programmable gate arrays. An overview of ways to describe digital circuits, an overview of HDL languages and other options. Basics of verilog language, methods of describing numerical systems, basics of language and syntax, Verilog - signals and data types, operators, attributes, testing Verilog - processes, clocks, flip-flops and registers, functions, procedures and packages Programmable gate arrays - principle of operation, IO pins and their properties, clock signals - oscillators, circuit configuration, programming tools, design principles. Analog output, digital modulation, PWM, Sigma-Delta. Memories, counters, PLLs and clock domains. State machines, advanced sequential circuits. IP, OpenCores and hardware with FPGA. Basics of Verilog and SystemVerilog, syntax, data types and signals Labs: Introduction to the issue of digital design, familiarization with development tools. Combinational logic circuits – practicing the syntax and basic constructions of the Verilog language Laboratory task - full adder, solution including testing Sequential logic circuits - ways of writing circuit behavior, processes and functions Laboratory task - counter Test No. 1 - Verification of knowledge of the first part of lectures and exercises. Analog output - digital modulation, PWM signal generation and more Laboratory task – sigma-delta modulator State machines – UART, I2C, communication with MCU Laboratory task – Application of UART and I2C bus

Conditions for subject completion

Part-time form (validity from: 2024/2025 Winter semester)
Task nameType of taskMax. number of points
(act. for subtasks)
Min. number of pointsMax. počet pokusů
Credit and Examination Credit and Examination 100 (100) 51
        Credit Credit 40 (40) 20
                Test č. 1 Written test 10  2 1
                Test č. 2 Written test 10  2 1
                Protokoly z laboratorních cvičení Laboratory work 20  10 1
        Examination Examination 60 (60) 15 3
                Písemná část zkoušky Written examination 40  10 1
                Ústní část zkoušky Oral examination 20  2 1
Mandatory attendence participation: Attendance on laboratory education (100%). Attendance on control tests. Report submission from laboratory exercises.

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Conditions for subject completion and attendance at the exercises within ISP: Completion of all mandatory tasks within individually agreed deadlines.

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Occurrence in study plans

Academic yearProgrammeBranch/spec.Spec.ZaměřeníFormStudy language Tut. centreYearWSType of duty
2024/2025 (N0714A060006) Applied Electronics K Czech Ostrava 1 Optional study plan
2024/2025 (N0714A060006) Applied Electronics P Czech Ostrava 1 Optional study plan

Occurrence in special blocks

Block nameAcademic yearForm of studyStudy language YearWSType of blockBlock owner

Assessment of instruction

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