450-4029/01 – Programmable Logic Devices (PHP)
Gurantor department | Department of Cybernetics and Biomedical Engineering | Credits | 4 |
Subject guarantor | Ing. Vladimír Kašík, Ph.D. | Subject version guarantor | Ing. Vladimír Kašík, Ph.D. |
Study level | undergraduate or graduate | Requirement | Optional |
Year | | Semester | winter |
| | Study language | Czech |
Year of introduction | 2010/2011 | Year of cancellation | 2020/2021 |
Intended for the faculties | FEI | Intended for study types | Follow-up Master |
Subject aims expressed by acquired skills and competences
The target of this subject is to familiarize students with today's development tools for high performance digital design.The contents of study corresponds with high density, high speed, low power and high reliability requirements of logic devices. The students will be able to choose appropriate development tools for any task and make a required design and implementation of combinatorial and sequential logic functions after passing that course. After that, they will be able to simulate projected design in logic simulator.
simulátoru. They can make the design as schematics, state diagram or VHDL.
Teaching methods
Lectures
Individual consultations
Experimental work in labs
Project work
Summary
The study covers the programmable logic devices design technique, especially of FPGA and CPLD types. An internal architecture is explained in some typical exaples. The design entry techniques include schematic designs, state diagrams and VHDL language. Some specific points of view are discussed: synchronous design, incremental design, hierarchical design, and more. Excercises are aimed to familiarize students with design entry, simulation and implementation tools. The students can verify their results on development boards in lab.
Compulsory literature:
Recommended literature:
Way of continuous check of knowledge in the course of semester
Verification of study:
1 test and 1 individual project
Conditions for credit:
The student is classifying on base 1 test 0-10 points and individual project 0-30 points. Closing Credit test - theoretical part 0-30 points, practical part 0-30 points, total 0-100 points. Total classification 51-100 points according study rules.
E-learning
Other requirements
There are not defined other requirements for student
Prerequisities
Subject has no prerequisities.
Co-requisities
Subject has no co-requisities.
Subject syllabus:
Lectures:
1. Programmable Logic Devices PAL, GAL. Comparison between HW and SW design of logic functions.
2. FPGA Xilinx architecture . Configurable Logic Blocks CLB, IOB, interconnect network.
3. FPGA and CPLD design tools. Introduction to Xilinx ISE development tool, schematic design, VHDL Language.
4. Basic Logic functions design - Logic Gates, Multiplexor, Decoder, Adder, Multiplexor.
5. Basic Sequential logic functions design - D-Flip Flop, Data Register, Shift Register, Counters.
6. Hierarchical Logic Design for FPGA.
7. State diagram as a tool for sequential logic function design. State editor. Applications in Embedded Control Systems.
8. Implementation of memories in FPGA. Block and Distributed RAM.
9. DSP Blocks in FPGA. Utilization in Medical Systems.
10. Design and utilization of IP Macros. Core Generator, EDK.
11. Specific features of FPGA architectures . DCM, HW multipliers...
12. Logic hazards and their elimination. Synchronous and asynchronous logic design.
13. Additional devices for logical system building with FPGA. Power supply and interconnecting devices.
Laboratories:
- Introduction of the content of excercises and credit requirements. Combinational and sequential logic functions .
- State machine example - security system, design and simulation.
- Synchronous logic design, clock signals, buffer GBUF. Hierarchical design, combined design. Treating LUT as memory, dual-ported memory, memory content definition.
- Test no.1: Programmable logic devices - basic terms, use, FPGA architecture . - Continuing on autonomous working. Design entry and simulation in VHDL.
- Continuing on autonomous working. Design implementation and tuning on development board.
- Seminar: Presentation of the individual projects.
Computer labs:
- Introduction with FPGA design tools.
- Xilinx ISE development software: Project navigator, editor VHDL.
- Continuing on the autonomous working.
- Xilinx ISE: Hierarchical design structure , logic buses, logic simulator, design implementation.
- Xilinx ISE: A serial interface implementation in FPGA.
- Logic function design based on state diagram. Functional evaluation in VHDL.
Conditions for subject completion
Occurrence in study plans
Occurrence in special blocks
Assessment of instruction