450-4029/03 – Programmable Logic Devices (PHP)
| Gurantor department | Department of Cybernetics and Biomedical Engineering | Credits | 4 |
| Subject guarantor | Ing. Vladimír Kašík, Ph.D. | Subject version guarantor | Ing. Vladimír Kašík, Ph.D. |
| Study level | undergraduate or graduate | Requirement | Optional |
| Year | | Semester | winter |
| | Study language | Czech |
| Year of introduction | 2018/2019 | Year of cancellation | 2022/2023 |
| Intended for the faculties | FEI | Intended for study types | Follow-up Master |
Subject aims expressed by acquired skills and competences
The target of this subject is to familiarize students with today's development tools for high performance digital design.The contents of study corresponds with high density, high speed, low power and high reliability requirements of logic devices. The students will be able to choose appropriate development tools for any task and make a required design and implementation of combinatorial and sequential logic functions after passing that course. After that, they will be able to simulate projected design in logic simulator.
simulátoru. They can make the design as schematics, state diagram or VHDL.
Teaching methods
Lectures
Individual consultations
Experimental work in labs
Project work
Summary
The study covers the programmable logic devices design technique, especially of FPGA and CPLD types. An internal architecture is explained in some typical exaples. The design entry techniques include schematic designs, state diagrams and VHDL language. Some specific points of view are discussed: synchronous design, incremental design, hierarchical design, and more. Excercises are aimed to familiarize students with design entry, simulation and implementation tools. The students can verify their results on development boards in lab.
Compulsory literature:
Recommended literature:
Additional study materials
Way of continuous check of knowledge in the course of semester
Verification of study:
5 tests of continuous control, 1 separate project.
Credit conditions: Students are classified on the basis of 5 tests 2-4 points, 1 separate project 10-20 points. Exam: - Written part - final test - 25 - 50 points. Oral part 5 - 10 points. Overall rating 51 - 100 points according to the study order.
E-learning
Other requirements
80% attendance in the course is also conditional upon granting the credit.
Prerequisities
Subject has no prerequisities.
Co-requisities
Subject has no co-requisities.
Subject syllabus:
Lectures:
1. Programmable Logic Devices PAL, GAL. Comparison between HW and SW design of logic functions.
2. FPGA Xilinx architecture . Configurable Logic Blocks CLB, IOB, interconnect network.
3. FPGA and CPLD design tools. Introduction to Xilinx ISE development tool, schematic design, VHDL Language.
4. Basic Logic functions design - Logic Gates, Multiplexor, Decoder, Adder, Multiplexor.
5. Basic Sequential logic functions design - D-Flip Flop, Data Register, Shift Register, Counters.
6. Hierarchical Logic Design for FPGA.
7. State diagram as a tool for sequential logic function design. State editor. Applications in Embedded Control Systems.
8. Implementation of memories in FPGA. Block and Distributed RAM.
9. DSP Blocks in FPGA. Utilization in Medical Systems.
10. Design and utilization of IP Macros. Core Generator, EDK.
11. Specific features of FPGA architectures . DCM, HW multipliers...
12. Logic hazards and their elimination. Synchronous and asynchronous logic design.
13. Additional devices for logical system building with FPGA. Power supply and interconnecting devices.
Laboratories:
1. Learning outcomes and competences for credit. Introduction to the Xilinx ISE development environment. Development board Nexys-3, -4. Project \"light snake\".
2. Xilinx ISE Development Environment: Project navigator, schematic design, HDL editor. Synthesis and implementation of the design.
3. Example of combinational logic circuit: arithmetic unit. Specify a separate task.
4. Synchronous design of logic systems, clock signal connection, GBUF driver.
5. Examples of sequential logic circuits. Counter design.
6. Xilinx ISE: Hierarchical design structure, bus, logic simulator, implementation of design. Timing simulation, timing analysis.
7. Implementation of state machine in FPGA. Continuing on a stand-alone task.
8. Xilinx ISE: Implementation of serial interface in FPGA.
9. Continue on a stand-alone task.
10. Continuing on a stand-alone task.
11. Design examples of basic functional blocks. Continuing on a stand-alone task.
12. Continuing on a stand-alone task. Implementation and debugging of a project on a development board.
13. Seminar: Presentation and defense of a separate project, granting of a credit.
Conditions for subject completion
Occurrence in study plans
Occurrence in special blocks
Assessment of instruction