454-0508/01 – Automated Design Environment (PAN)

Gurantor departmentDepartment of TelecommunicationsCredits4
Subject guarantordoc. Ing. Jaroslav Zdrálek, Ph.D.Subject version guarantordoc. Ing. Jaroslav Zdrálek, Ph.D.
Study levelundergraduate or graduateRequirementOptional
Year3Semesterwinter
Study languageCzech
Year of introduction1999/2000Year of cancellation2009/2010
Intended for the facultiesFEIIntended for study typesBachelor
Instruction secured by
LoginNameTuitorTeacher giving lectures
ZDR20 doc. Ing. Jaroslav Zdrálek, Ph.D.
Extent of instruction for forms of study
Form of studyWay of compl.Extent
Full-time Credit and Examination 2+2
Combined Credit and Examination 2+8

Subject aims expressed by acquired skills and competences

Understand the computer digital circuit design and method of verification. Learning outcomes are set so that the students are able to identify and apply tasks in the field of digital circuit design in automated design environment.

Teaching methods

Lectures
Tutorials
Experimental work in labs

Summary

Modern digital system design proceeding, where design is described by means of programmable language resources VHDL as are entities, architectures, configuration, packets and libraries. Circuit description manners upon circuit function basis knowledge, data-flow description and structural, suggested circuit division possibilities. Entry for combinational and sequential logical circuit. Manners for testing proposal.

Compulsory literature:

Bhasker J.: A VHDL Primer, Revised edition; Prantice Hall 1994, ISBN 0-13-1814447-8 Bhasker J.: A VHDL Primer, Third edition; Prantice Hall 1999, ISBN 0-13-096575-8 Pedroni V.: Digital Electronics and Design with VHDL; Morgan Kaufmann (January 18, 2008); ISBN-10: 0123742706; ISBN-13: 978-0123742704 Ashenden P. J: The Designer's Guide to VHDL, Volume 3, Third Edition (Systems on Silicon); Morgan Kaufmann; 3 edition (May 16, 2008); ISBN-10: 0120887851; ISBN-13: 978-0120887859 Pedroni V. A.: Circuit Design with VHDL; The MIT Press (August 1, 2004); ISBN-10: 0262162245; ISBN-13: 978-0262162241 Botros N. M.: HDL Programming Fundamentals: VHDL and Verilog (Davinci Engineering); Charles River Media; 1 edition (November 18, 2005); ISBN-10: 1584508558; ISBN-13: 978-1584508557 Chu Pong P.: RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability; Wiley-IEEE Press (April 14, 2006); ISBN-10: 0471720925; ISBN-13: 978-0471720928

Recommended literature:

IEEE Stdandard VHDL Language Ref. Manual. IEEE Std 1076-1993 Pedroni V.: Digital Electronics and Design with VHDL; Morgan Kaufmann (January 18, 2008); ISBN-10: 0123742706; ISBN-13: 978-0123742704 Ashenden P. J: The Designer's Guide to VHDL, Volume 3, Third Edition (Systems on Silicon); Morgan Kaufmann; 3 edition (May 16, 2008); ISBN-10: 0120887851; ISBN-13: 978-0120887859 Pedroni V. A.: Circuit Design with VHDL; The MIT Press (August 1, 2004); ISBN-10: 0262162245; ISBN-13: 978-0262162241 Botros N. M.: HDL Programming Fundamentals: VHDL and Verilog (Davinci Engineering); Charles River Media; 1 edition (November 18, 2005); ISBN-10: 1584508558; ISBN-13: 978-1584508557 Chu Pong P.: RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability; Wiley-IEEE Press (April 14, 2006); ISBN-10: 0471720925; ISBN-13: 978-0471720928 Armstrong J. A.: Chip-level modeling with VHDL, Prentice Hall, 1989, ISBN 0-13-133190-6 Coehlo D. R.: The VHDL Handbook, Kluwer Academic Publisher, 1992, ISBN 0-7923 9031-8

Way of continuous check of knowledge in the course of semester

Podmínky udělení zápočtu: Maximální počet bodů ze cvičení je 44 bodů. K udělení zápočtu je zapotřebí 10 bodů.

E-learning

Další požadavky na studenta

Prerequisities

Subject has no prerequisities.

Co-requisities

Subject has no co-requisities.

Subject syllabus:

Lectures: Introduction to environment VHDL, fundamental names, entity and architecture. Fundamental elements of VHDL, data types, operations. Sequence modeling - 1st part. Sequence modeling - 2nd part. Dataflow modeling. Structural modeling. Configurations. Generic variable and configurations. Design testing. File. Subprograms. Libraries. Model simulation. Examples of VHDL. Projects: Design of simple digital system. Computer labs: Working with IDE system. Safety training. Working with IDE system. Sequence programming. Dataflow model Models of basic logic elements. Models of basic logic elements. Structural programming. Models of sequence logic circuits. Testing of design. Solution of individual design. Solution of individual design. Solution of individual design. Solution of individual design. Solution of individual design.

Conditions for subject completion

Full-time form (validity from: 1960/1961 Summer semester)
Task nameType of taskMax. number of points
(act. for subtasks)
Min. number of points
Exercises evaluation and Examination Credit and Examination 100 (100) 51
        Exercises evaluation Credit 44 (44) 0
                Design of combinational digital system Project 20  0
                Design of sequence digital system Project 24  5
        Examination Examination 56 (56) 0
                Oral Oral examination 56  0
Mandatory attendence parzicipation:

Show history

Occurrence in study plans

Academic yearProgrammeField of studySpec.FormStudy language Tut. centreYearWSType of duty
2009/2010 (B2645) Electrical Engineering, Communication and Computer Systems (2612R018) Electronics and Communication Technology P Czech Ostrava 2 Choice-compulsory study plan
2009/2010 (B2647) Information and Communication Technology (1103R031) Computational Mathematics P Czech Ostrava 3 Optional study plan
2009/2010 (B2647) Information and Communication Technology (2601R013) Telecommunication Technology P Czech Ostrava 3 Optional study plan
2009/2010 (B2647) Information and Communication Technology (2612R025) Computer Science and Technology P Czech Ostrava 3 Optional study plan
2009/2010 (B2647) Information and Communication Technology (2612R059) Mobile Technology P Czech Ostrava 3 Optional study plan
2009/2010 (B2645) Electrical Engineering, Communication and Computer Systems (2612R018) Electronics and Communication Technology K Czech Ostrava 2 Choice-compulsory study plan
2009/2010 (B2647) Information and Communication Technology (1103R031) Computational Mathematics K Czech Ostrava 3 Optional study plan
2009/2010 (B2647) Information and Communication Technology (2601R013) Telecommunication Technology K Czech Ostrava 3 Optional study plan
2009/2010 (B2647) Information and Communication Technology (2612R025) Computer Science and Technology K Czech Ostrava 3 Optional study plan
2009/2010 (B2647) Information and Communication Technology (2612R059) Mobile Technology K Czech Ostrava 3 Optional study plan
2008/2009 (B2645) Electrical Engineering, Communication and Computer Systems (2612R018) Electronics and Communication Technology P Czech Ostrava 2 Choice-compulsory study plan
2008/2009 (B2645) Electrical Engineering, Communication and Computer Systems (2612R018) Electronics and Communication Technology K Czech Ostrava 2 Choice-compulsory study plan
2008/2009 (B2647) Information and Communication Technology (1103R031) Computational Mathematics P Czech Ostrava 3 Optional study plan
2008/2009 (B2647) Information and Communication Technology (2601R013) Telecommunication Technology P Czech Ostrava 3 Optional study plan
2008/2009 (B2647) Information and Communication Technology (2612R025) Computer Science and Technology P Czech Ostrava 3 Optional study plan
2008/2009 (B2647) Information and Communication Technology (2612R059) Mobile Technology P Czech Ostrava 3 Optional study plan
2008/2009 (B2647) Information and Communication Technology (1103R031) Computational Mathematics K Czech Ostrava 2 Optional study plan
2008/2009 (B2647) Information and Communication Technology (2601R013) Telecommunication Technology K Czech Ostrava 2 Optional study plan
2008/2009 (B2647) Information and Communication Technology (2612R025) Computer Science and Technology K Czech Ostrava 2 Optional study plan
2008/2009 (B2647) Information and Communication Technology (2612R059) Mobile Technology K Czech Ostrava 2 Optional study plan
2007/2008 (B2645) Electrical Engineering, Communication and Computer Systems (2612R018) Electronics and Communication Technology P Czech Ostrava 2 Choice-compulsory study plan
2007/2008 (B2645) Electrical Engineering, Communication and Computer Systems (2612R018) Electronics and Communication Technology K Czech Ostrava 2 Choice-compulsory study plan
2007/2008 (B2647) Information and Communication Technology (1103R031) Computational Mathematics P Czech Ostrava 3 Optional study plan
2007/2008 (B2647) Information and Communication Technology (2601R013) Telecommunication Technology P Czech Ostrava 3 Optional study plan
2007/2008 (B2647) Information and Communication Technology (2612R025) Computer Science and Technology P Czech Ostrava 3 Optional study plan
2007/2008 (B2647) Information and Communication Technology (2612R059) Mobile Technology P Czech Ostrava 3 Optional study plan
2007/2008 (B2647) Information and Communication Technology (1103R031) Computational Mathematics K Czech Ostrava 3 Optional study plan
2007/2008 (B2647) Information and Communication Technology (2601R013) Telecommunication Technology K Czech Ostrava 3 Optional study plan
2007/2008 (B2647) Information and Communication Technology (2612R025) Computer Science and Technology K Czech Ostrava 3 Optional study plan
2007/2008 (B2647) Information and Communication Technology (2612R059) Mobile Technology K Czech Ostrava 3 Optional study plan
2006/2007 (B2645) Electrical Engineering, Communication and Computer Systems (2612R018) Electronics and Communication Technology P Czech Ostrava 2 Choice-compulsory study plan
2006/2007 (B2645) Electrical Engineering, Communication and Computer Systems (2612R018) Electronics and Communication Technology K Czech Ostrava 2 Choice-compulsory study plan
2006/2007 (B2647) Information and Communication Technology (1103R031) Computational Mathematics P Czech Ostrava 3 Optional study plan
2006/2007 (B2647) Information and Communication Technology (2601R013) Telecommunication Technology P Czech Ostrava 3 Optional study plan
2006/2007 (B2647) Information and Communication Technology (2612R025) Computer Science and Technology P Czech Ostrava 3 Optional study plan
2006/2007 (B2647) Information and Communication Technology (2612R059) Mobile Technology P Czech Ostrava 3 Optional study plan
2006/2007 (B2647) Information and Communication Technology (1103R031) Computational Mathematics K Czech Ostrava 3 Optional study plan
2006/2007 (B2647) Information and Communication Technology (2601R013) Telecommunication Technology K Czech Ostrava 3 Optional study plan
2006/2007 (B2647) Information and Communication Technology (2612R025) Computer Science and Technology K Czech Ostrava 3 Optional study plan
2006/2007 (B2647) Information and Communication Technology (2612R059) Mobile Technology K Czech Ostrava 3 Optional study plan
2005/2006 (B2645) Electrical Engineering, Communication and Computer Systems (2612R018) Electronics and Communication Technology P Czech Ostrava 2 Choice-compulsory study plan
2005/2006 (B2645) Electrical Engineering, Communication and Computer Systems (2612R018) Electronics and Communication Technology K Czech Ostrava 2 Choice-compulsory study plan
2004/2005 (B2645) Electrical Engineering, Communication and Computer Systems (2612R018) Electronics and Communication Technology P Czech Ostrava 2 Choice-compulsory study plan
2004/2005 (B2645) Electrical Engineering, Communication and Computer Systems (2612R018) Electronics and Communication Technology K Czech Ostrava 2 Choice-compulsory study plan
2003/2004 (B2645) Electrical Engineering, Communication and Computer Systems (2612R018) Electronics and Communication Technology P Czech Ostrava 2 Choice-compulsory study plan
2003/2004 (B2645) Electrical Engineering, Communication and Computer Systems (2612R018) Electronics and Communication Technology K Czech Ostrava 2 Choice-compulsory study plan

Occurrence in special blocks

Block nameAcademic yearForm of studyStudy language YearWSType of blockBlock owner