455-0094/01 – Programmable Logic Devices (PHP)

Gurantor departmentDepartment of Measurement and ControlCredits4
Subject guarantorIng. Vladimír Kašík, Ph.D.Subject version guarantorIng. Vladimír Kašík, Ph.D.
Study levelundergraduate or graduateRequirementChoice-compulsory
YearSemestersummer
Study languageCzech
Year of introduction2002/2003Year of cancellation2002/2003
Intended for the facultiesFEIIntended for study typesMaster
Instruction secured by
LoginNameTuitorTeacher giving lectures
KAS73 Ing. Vladimír Kašík, Ph.D.
Extent of instruction for forms of study
Form of studyWay of compl.Extent
Full-time Credit and Examination 2+3

Subject aims expressed by acquired skills and competences

The target of this subject is to familiarize students with today's development tools for high performance digital design. The contents of study corresponds with high density, high speed, low power and high reliability requirements of logic devices. The students will be able to choose appropriate development tools for any task and make a required design and implementation of combinatorial and sequential logic functions after passing that course. After that, they will be able to simulate projected design in logic simulator. simulátoru. They can make the design as schematics, state diagram or VHDL.

Teaching methods

Summary

The target of this subject is to familiarize students with today's development tools for high performance digital design. The contents of study corresponds with high density, high speed, low power and high reliability requirements of logic devices. The students will be able to choose appropriate development tools for any task and make a required design and implementation of combinatorial and sequential logic functions after passing that course. After that, they will be able to simulate projected design in logic simulator. simulátoru. They can make the design as schematics, state diagram or VHDL. The study covers the programmable logic devices design technique, especially of FPGA and CPLD types. An internal architecture is explained in some typical exaples. The design entry techniques include schematic designs, state diagrams and VHDL language. Some specific points of view are discussed: synchronous design, incremental design, hierarchical design, and more. Excercises are aimed to familiarize students with design entry, simulation and implementation tools. The students can verify their results on development boards in lab.

Compulsory literature:

The Programmable Logic Databook , Xilinx Inc., 1999. Berge, J.: VHDL Designer's Reference. Dordrecht, Kluwer Academic, 1992. Mirkowski, J. - Kapustka,M. - Skowroński, Z. - Biniszkiewicz, A.: EVITATM Interactive VHDL Tutorial REV.2.1. Henderson, ALDEC, Inc., 1998.

Recommended literature:

Way of continuous check of knowledge in the course of semester

Verification of study: 1 test, 2 autonomous works Conditions for credit: 20 - 40 points

E-learning

Další požadavky na studenta

Prerequisities

Subject has no prerequisities.

Co-requisities

Subject has no co-requisities.

Subject syllabus:

Lectures: Programmable Logic Devices PAL, GAL. Comparison between HW and SW design of logic functions. FPGA Xilinx series 4000 architecture . Configurable Logic Blocks CLB, IOB, interconnect network. FPGA design tools. Xilinx Foundation: schematic editor, LogiBLOX. Simulation and implementation of logic design. The creation of a configuration file, tuning. Logic functions design - VHDL. Design structure, entity, signal, data types. Combinational logic functions design in VHDL. Concurrent assignment, multiplexor, delay. Sequential logic functions design in VHDL. Process, variable, synchronization. State diagram as a tool for sequential logic function design. State editor. Logic hazards and their elimination. Synchronous and asynchronous logic design. Specific features of FPGA architectures . Incremental design, EPIC. Programmable logic devices Xilinx 5200, 9500 and Virtex series. Standard IEEE 1149.1 Boundary-Scan. Additional devices for logical system building with FPGA. Power supply and interconnecting devices. Other PLD architectures (Altera, Lattice, _). Designing of some standard macro-blocks in FPGA. Microprocessor core. Exercises: Introduction of the content of excercises and credit requirements. Combinational and sequential logic functions . Test no.1: Programmable logic devices - basic terms, use, XC4000 architecture . Setting of the 1-st autonomous working: Design entry, simulation and implementation of logic system with VHDL. Seminar: Presentation of the 2-nd autonomous working. Laboratories: Continuing on the 1-st autonomous working. State machine example - security system, design and simulation. Synchronous logic design, clock signals, buffer GBUF. Hierarchical design, combined design. Treating LUT as memory, dual-ported memory, memory content definition. Continuing on autonomous working. Design entry and simulation in VHDL. Continuing on autonomous working. Design implementation and tuning on development board. Computer labs: Introduction with FPGA design tools. Xilinx Foundation development software: Schematic editor, device library, LogiBLOX. Xilinx Foundation: Hierarchical design structure , logic buses, logic simulator, design implementation. Xilinx Foundation: functional and timing simulation, timing analysis, EPIC. A serial interface implementation in FPGA. Presentation of the 1-st autonomous working. Logic function design based on state diagram. Functional evaluation in VHDL.

Conditions for subject completion

Full-time form (validity from: 1960/1961 Summer semester)
Task nameType of taskMax. number of points
(act. for subtasks)
Min. number of points
Exercises evaluation and Examination Credit and Examination 100 (145) 51
        Examination Examination 100  0
        Exercises evaluation Credit 45  0
Mandatory attendence parzicipation:

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Occurrence in study plans

Academic yearProgrammeField of studySpec.FormStudy language Tut. centreYearWSType of duty
2002/2003 (M2612) Electrical Engineering and Computer Science (2601T004) Measurement and Control Engineering P Czech Ostrava Choice-compulsory study plan
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2002/2003 (M2612) Electrical Engineering and Computer Science (3902T023) Computer Science P Czech Ostrava Choice-compulsory study plan
2002/2003 (M2612) Electrical Engineering and Computer Science (3907T001) Electrical Power Engineering P Czech Ostrava Choice-compulsory study plan
2002/2003 (M2612) Electrical Engineering and Computer Science (2601T004) Measurement and Control Engineering P Czech Ostrava 4 Optional study plan

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