455-0917/01 – Diagnostics of Electronic Circuits ()

Gurantor departmentDepartment of Measurement and ControlCredits0
Subject guarantorprof. Ing. Karel Vlček, CSc.Subject version guarantorprof. Ing. Karel Vlček, CSc.
Study levelpostgraduateRequirementChoice-compulsory
YearSemesterwinter + summer
Study languageCzech
Year of introduction1960/1961Year of cancellation2005/2006
Intended for the facultiesFEIIntended for study typesDoctoral
Extent of instruction for forms of study
Form of studyWay of compl.Extent
Full-time Credit and Examination 2+0
Combined Credit and Examination 2+0

Subject aims expressed by acquired skills and competences

Teaching methods

Summary

The Computer Diagnostics arose from the same moment as the beginning of computer design. The necessity of verification of behavioural of circuits is regular process of design, and manufacturing, fault discovering on the basis of errors found by the test process is the substantial activity in circuit debugging and computer assembling, as well as in services. The testing is the practical application of diagnostics, it is necessary to fault discovering from the errors indicated as the responses of fault circuit. They are not in congruency with the description of technical specification. The increasing circuit complexity of computers causes the necessity to apply the sophisticate methods of testing. Minimisation of the length of test vector sequences, together with clever way of error detection through the test processing are the basic assumptions for effective testing, namely in these cases, if it is used pseudo-random test generation. Application of response compression by the method of signature analysis during the test results evaluation is very carefully worked out test method, which is contained as the part of Boundary-Scan Test methodology defined by IEEE Std. 1149.1. The BSDL language does the support of the circuit design. Frequently asked parts of digital systems are tests of memories, they are with respect to more complicate model of failure and with respect to regular structure of memory chip, generated by algorithmic ways. Statistic evaluation of failure occurrence and the effective capture of errors during the tests complete the overview of test methods of semiconductor memories. Specific requirements for test machine construction of memories are introduced in this coherence. The extra chapter is devoted to memory dynamic parameter testing. Briefly introduced are methods of on-line testing with the support of error-control coding of written files in memories.

Compulsory literature:

Recommended literature:

Way of continuous check of knowledge in the course of semester

Průběžná kontrola studia: Zpracování samostatného projektu

E-learning

Další požadavky na studenta

Prerequisities

Subject has no prerequisities.

Co-requisities

Subject has no co-requisities.

Subject syllabus:

Přednášky: Základní pojmy diagnostiky. Druhy poruch v číslicových obvodech.Detekce a lokalizace poruch. Diagnostické testy. Modely poruch. Příčiny poruch v číslicových systémech. Poruchy t0, tl detekce poruch t. Poruchy typu z (zkrat). Projevy poruch typu z. Vícenásobné poruchy. Generování testů. D-algoritmus. Boolovské diference. Intuitivní zcitlivění cesty. Metoda zcitlivění cesty bez větvení a s větvením. Použití D-algoritmu. Detekce poruch na primárních vstupech obvodu a na vnitřních vodičích obvodu. Booleovské diference vyšších řádů. Pseudonáhodné generování testů. Testy pro sekvenční obvody. Reedovy-Mullerovy rozvoje. Posuvné registry s lineárními zpětnými vazbami. Maticový popis. Univerzální generátor pseudonáhodných posloupností. Komprese diagnostických dat. Příznaková analýza. Výpočet pravděpodobnosti ztráty chyby. Návrh pro usnadnění testování. Strukturovaný návrh, vývoj a uspořádání. Heuristické diagnostické postupy. Hraniční snímání a testování: Boundary-Scan Testing. Architektura B-ST registrů. Rozhraní TAP. Řadič TAP. Instrukce řadiče. Popis činností instrukcí. Programovací jazyk BSDL. Sériový formát testovacích dat. Systémová diagnostika. Testování pamětí a PLD modely poruch.Testování kabeláže a plošných spojů. Architektura, programování a diagnostika PLD a FPGA. Diagnostika počítačových systémů. Testy pamětí n, n2 a n3/2. Expertní diagnostické systémy. Testování systémů se smíšenými signály. Standard IEEE Std 1149.4. Zkoušeče integrovaných obvodů, neosazených i osazených desek a kabeláže. Průběžná diagnostika. Systémy odolné proti poruchám. Zabezpečení proti poruchám, dvoudrátová logika, bezpečné systémy. Zálohování, obvodová a programová implementace odolných systémů.

Conditions for subject completion

Full-time form (validity from: 1960/1961 Summer semester, validity until: 2012/2013 Summer semester)
Task nameType of taskMax. number of points
(act. for subtasks)
Min. number of points
Exercises evaluation and Examination Credit and Examination 100 (145) 51
        Examination Examination 100  0
        Exercises evaluation Credit 45  0
Mandatory attendence parzicipation:

Show history

Occurrence in study plans

Academic yearProgrammeField of studySpec.FormStudy language Tut. centreYearWSType of duty
2005/2006 (P2645) Electrical Engineering, Communication and Computer systems (2612V015) Electronics P Czech Ostrava Choice-compulsory study plan
2004/2005 (P2645) Electrical Engineering, Communication and Computer systems (2612V015) Electronics P Czech Ostrava Choice-compulsory study plan
2003/2004 (P2645) Electrical Engineering, Communication and Computer systems (2612V015) Electronics P Czech Ostrava Choice-compulsory study plan
2002/2003 (P2612) Electrical Engineering and Computer Science (2612V015) Electronics P Czech Ostrava Choice-compulsory study plan
2001/2002 (P2612) Electrical Engineering and Computer Science (2612V015) Electronics P Czech Ostrava Choice-compulsory study plan

Occurrence in special blocks

Block nameAcademic yearForm of studyStudy language YearWSType of blockBlock owner